1. Field of the Invention
The present invention relates to a failure analysis method, a failure analysis system, and a memory macro system.
2. Description of the Related Art
Conventionally, in a memory macro incorporated a system LSI, there is a method of specifying a failed bit position (failed memory cell) using a fail bit map (FBM) thereof. To display the FBM, an electrical test result is first detected by a tester for each memory cell. It is a general procedure that one-dimensional array information (logical address) corresponding to a collection order of the electrical test results acquired by the tester is converted to a two-dimensional coordinate value (physical address) associated with a physical layout of the memory cell in the memory macro on a wafer, thereby displaying position information of the failed memory cell ascertained by the electrical test result in a display area such as a display device (for example, see Japanese Patent No. 3256555).
As one type of the memory macro, there is a static random access memory (SRAM) of a type having a spare cell other than normal cells and capable of performing a relieving process such that when a failure is found in one of the normal cells by a failure check based on an electrical test result prior to shipment, the normal cell having a failure is replaced by the spare cell. From the SRAM having such a spare cell, before a relieving process, only electrical test results of normal cells, and after the relieving process, only electrical test results of normal cells excluding the spare cell and the failed cell replaced by the spare cell can be collected. Therefore, if the logical address of the failed memory cell acquired by the electrical test result from the SRAM having the spare cell is converted to a physical address to display the failed memory cell, it is necessary to change interpretation of the position of the failed memory cell displayed on an FBM according to whether it is before or after the relieving process and which memory cell has been relieved. This can be a complicated process to the users. If there is a mistake in the interpretation of the position of the failed memory cell at the time of performing a physical failure analysis (PFA) based on the FBM, a wrong analysis position will be obtained.